As a clock frequency dividing circuit which divides a frequency of a clock signal having an arbitrary frequency to generate a clock signal having a lower frequency, a frequency dividing circuit (an integral frequency dividing circuit) in which a frequency dividing ratio, that is, a ratio of a frequency of a clock signal before divided to a frequency of a clock signal after divided is 1/M (M is an integer) can be easily achieved by using a counter circuit.
On the other hand, a frequency dividing circuit (a rational frequency dividing circuit) being capable of dividing even if a frequency dividing ratio is N/M (N and M are integers) is proposed (Patent Document 1 and Patent Document 2, for example).
According to these related arts, a value set to numerator of a frequency dividing ratio (the value N in the frequency dividing ratio N/M) is cumulatively added at every cycle of an input clock signal, and when the addition result becomes larger than a value set to denominator of a frequency dividing ratio (the value M in the frequency dividing ratio N/M), rational frequency division is achieved by performing an operation to subtract M from the addition result and then by picking the pulse of the input clock signal appropriately with reference to the addition result.
In addition, as another related art, a clock generating circuit using a phase interpolator is proposed (Patent Document 3, for example). According to Patent Document 3, the phase interpolator makes it possible to generate edge at a timing other than a timing of the edge of an input clock signal. Therefore, it is possible to generate a rational frequency-divided clock signal having a constant cycle time.    Patent Document 1: Japanese Patent Application Laid-open No. 2005-045507    Patent Document 2: Japanese Patent Application Laid-open No. 2006-148807    Patent Document 3: Japanese Patent Application Laid-open No. 2002-057578